Synchronous Sampling

A regular oscilloscope has an internal time-base which defines when samples of the power trace are taken.

Power analysis is about measuring how power as a target performs certain operations. Fundamentally, these operations occur relative to a clock on the target. When capturing with an oscilloscope, there is some changing delay between the device clock and the next sample point.

With an oscilloscope, you need to sample at a high rate to reduce this delay (jitter). ChipWhisperer instead uses a synchronous sampling method, which generates a sample clock —perfectly locked to the target device clock. It allows you to multiply and phase-shift the sample clock, while still maintaining consistent time alignment.

Fig 1: The time delay between the device clock rising edge and sample point (red circles on power trace) varies, as there is no phase relationship between the oscilloscope timebase and the device clock. This requires running the oscilloscope at fast sample rates (5x-10x device clock speed) to reduce the potential phase jitter.

Fig 2: ChipWhisperer maintains a constant phase relationship between the two clocks. The sample clock can still run faster than the device clock (here running 2x as fast), but the sample points are always at consistent locations within the device clock cycles. This allows ChipWhisperer hardware to be effective at only 1x to 4x the device clock rate.

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